Senior Wireless Engineer

Employer description

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

As a Senior Wireless Engineer, you will turn our modem and waveform designs into real, deployable hardware. Working directly under our Senior Wireless Systems Engineer II, you will take MATLAB/Simulink models of the physical layer and implement them as bit-true, fixed-point designs in C and RTL for our FPGAs and SoCs. You will own fixed-point conversion, verification against the golden reference, and FPGA timing and resource optimization — getting real waveforms onto our drones and working over the air.

Responsibilities

• Implement modem and physical-layer blocks — modulation/demodulation, synchronization, equalization, and channel coding/FEC — from MATLAB/Simulink models into RTL (Verilog/VHDL) and embedded C
• Own fixed-point conversion from floating-point models, analyzing quantization, precision, and dynamic-range trade-offs
• Build bit- and cycle-accurate testbenches that verify RTL and C implementations against the MATLAB/Simulink golden reference
• Close timing and optimize LUT, DSP, and BRAM utilization on Xilinx/AMD (or Intel) FPGAs and SoCs
• Partition the signal chain between FPGA fabric and embedded processor, co-designing the hardware/software boundary
• Debug the physical layer on captured and live signals alongside the communication systems, RF, and firmware teams, working directly with the Principal Communications Systems Engineer to take waveforms from model to silicon

You should have the following

• Bachelor of Science in Electrical Engineering, Computer Engineering, or a related field required; Master's degree highly preferred
• 7+ years implementing DSP or communications algorithms in RTL (Verilog/VHDL) and/or embedded C for FPGA or SoC targets
• Strong DSP and digital communications fundamentals: modulation, synchronization, equalization, filtering, and FEC/channel coding
• Demonstrated experience with fixed-point conversion and bit-true implementation from MATLAB/Simulink models
• Proficiency with the FPGA design flow: simulation, synthesis, timing closure, and resource optimization (Vivado/Vitis or Quartus)
• Experience building testbenches and verifying implementations against a golden reference model

Nice to have

• Model-Based Design: Generating or hand-optimizing HDL and C from Simulink using MATLAB HDL Coder and Embedded Coder
• Wireless Modems: Hands-on implementation of an end-to-end modem (OFDM, spread spectrum, or single-carrier) that shipped in hardware
• SoC Integration: Zynq, RFSoC, or similar SoCs, including AXI interfaces and hardware/software co-design
• RF/SDR Familiarity: Understanding of the RF front-end, data converters (ADC/DAC), and software-defined radio pipelines
• Advanced FEC: Hardware implementation of LDPC, Turbo, Viterbi, or Reed-Solomon decoders

US Salary Range

$187,000 – $261,500 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.

We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.