Eliyan
PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |
Bay Area · On-site · Senior
- Discipline
- Hardware
- Industry
- Semiconductor
Spec sheet
Automatically summarized from the employer’s posting. Check the original description below for full requirements.
Engineering
Sr Staff / Principal CAD & Design Methodology Engineer to architect RTL-to-GDSII flows and design infra for advanced SoCs; leads multi-vendor/multi-foundry methodology platforms and scalable tapeouts across Intel/TSMC/Samsung/GlobalFoundries.
Required
- RTL-to-GDSII
- design methodology
- multi-vendor design flows
- SoC implementation
- low-power chiplet
- tapeouts
- R2G system architecture
- multi-foundry nodes
Preferred
- multi-foundry experience
- advanced node methodology
- CAD/EDA tooling
- hierarchical implementation
- power integrity
- floorplanning
- timing closure
Employer description
ABOUT THE ROLE
As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.
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