Intel
EDA Tools Hardware Engineer
Santa Clara, CA and 3 more · On-site · Senior
Sites: Santa Clara, CA, Hillsboro, OR, Folsom, CA, Austin, TX
- Discipline
- Hardware
- Industry
- Semiconductor
Spec sheet
Automatically summarized from the employer’s posting. Check the original description below for full requirements.
Hardware-focused EDA Tools Engineer role in US locations (Santa Clara, Folsom, Hillsboro, Austin) working on full-chip physical design flows and tool integration for Intel SoC pipelines.
$141,910–$269,100 / year · Equity · 6+ years · Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field
Required
- Full-chip physical implementation flows
- Innovus
- Clock tree synthesis (CTS)
- Placement and routing
- Power grid design/IR drop concepts
- STA (preferred)
- Scripting in Linux (preferred)
Preferred
- Static timing analysis (STA)
- Power grid design
- Experience with large SoC or multi-block design
- Automation scripting in Linux
- Experience with SoC flows
Benefits
- medical
- 401k
- vacation
Employer description
Job Details:
Job Description: The Role and Impact
Join Intel’s world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will have the unique opportunity to collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.
Key Responsibilities
Full Chip Implementation Flow Development
Develop and maintain full-chip physical implementation flows including:
Floor planning and partitioning strategies
Hierarchical block integration
Chip-level placement and routing coordination
Power grid planning and analysis
Clock tree synthesis (CTS) strategy integration
Enable scalable SoC assembly flows for multi-block and multi-power domain designs.
Define methodology for hierarchical design reuse and integration
Qualifications:Minimum Qualifications
Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master’s degree with 4+ years of experience; or a PhD with 2+ years of experience
Physical design fundamentals (I.e. placement, routing)
Clock tree synthesis (CTS)
Full-chip integration methodologies using Innovus
Preferred Qualifications
Static timing analysis (STA)
Power grid design and IR drop concepts
Experience with large SoC or multi-block design implementation flows
Experience scripting and automation skills in Linux environments
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, California, Santa Clara
Additional Locations:US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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