Principal/Sr. Principal FPGA Engineer

Employer description

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE REQUIRED FOR START: Yes

CLEARANCE TYPE: Secret

TRAVEL: Yes, 10% of the TimeDescription

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people’s lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation’s history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they’re making history.

We are seeking talented Principal and Sr. Principal FPGA Design Engineers to join our growing team in Rolling Meadows, IL.

The Multidomain Sensing, Targeting, and Survivability Division (MSTS), located in the Northwest Chicago suburbs, develops operational Electronic Warfare (EW) and targeting systems that provide situational awareness, self-protection, and offensive electronic attack capability to platforms across the spectrum from visible light IR to millimeter wave RF. By joining us, you’ll work on projects that help safeguard our nation related to land forces, rotary wing survivability systems, international and U.S. military electronic warfare systems, communications systems, missile warning systems and sensors, infrared counter-measure systems (IRCM), automatic test equipment, modeling and simulation, and situational awareness programs.

As a Principal / Sr. Principal FPGA Design Engineer, you will join a diverse, high-performing team responsible for the end-to-end development of advanced RF and EO/IR products. You will contribute across the FPGA development lifecycle, including requirements analysis and refinement, system and FPGA architecture, RTL design and coding, testbench development, verification, synthesis, implementation, timing closure, hardware integration, qualification, production support, and troubleshooting.

You will develop FPGA-based digital subsystems integrated into circuit card assemblies, working closely with systems, software, hardware, and integration & test engineers. Designs utilize FPGA technologies from major vendors including AMD Xilinx, Intel FPGA, and Microchip, and support high-speed interfaces, RF and EO/IR signal-processing chains, controls, data links, embedded processing, and processor interfaces.

This position will be full-time and on-site at our Rolling Meadows, IL. location.

This position may be filled at either the Principal or Sr. Principal level based on the qualifications below.

Basic Qualifications for Principal FPGA Design Engineer

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline with a minimum of 5 years of relevant FPGA/ASIC design experience; or a master’s degree with a minimum of 3 years of relevant experience; or a PhD with relevant experience.Proficiency in VHDL, Verilog, or SystemVerilog for synthesizable RTL design.Experience translating system performance and operational requirements into FPGA architecture, detailed requirements, interfaces, implementation, and verification criteria.Experience developing synchronous RTL, including state machines, pipelined data paths, clock and reset architectures, and designs with multiple clock domains.Experience developing and executing self-checking RTL test benches and requirements-based verification cases.Proficiency with the full FPGA development flow, including RTL simulation, synthesis, place and route, static timing analysis, and power analysis.Experience reviewing synthesis, utilization, design-rule, and timing reports and resolving implementation and timing-closure issues.Experience with at least one major FPGA device architecture and its associated development toolchain, such as AMD Xilinx devices with Vivado or Intel FPGA devices with Quartus, and related FPGA EDA tools such as ModelSim/QuestaSim or Synplify.Experience using Python, Tcl, C/C++, or other scripting/programming languages for automation, verification, data generation, or report analysis.Experience integrating and troubleshooting FPGA designs in simulation and laboratory hardware.Ability to develop FPGA designs with minimal supervision, communicate technical status and risks proactively, participate in technical reviews, and work effectively across engineering disciplines.U.S. citizenship.Must have interim Secret clearance prior to starting.  Once started, must have the ability to obtain and maintain a Secret security clearance. 

Basic Qualifications for Sr. Principal FPGA Design Engineer

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline with a minimum of 8 years of relevant FPGA/ASIC design experience; or a master’s degree with a minimum of 6 years of relevant experience; or a PhD with a minimum of 4 years of relevant experience.Proficiency in VHDL, Verilog, or SystemVerilog for synthesizable RTL design.Experience translating system performance and operational requirements into FPGA architecture, detailed requirements, interfaces, implementation, and verification criteria.Experience developing synchronous RTL, including state machines, pipelined data paths, clock and reset architectures, and designs with multiple clock domains.Experience developing and executing self-checking RTL test benches and requirements-based verification cases.Proficiency with the full FPGA development flow, including RTL simulation, synthesis, place and route, static timing analysis, and power analysis.Experience reviewing synthesis, utilization, design-rule, and timing reports and resolving implementation and timing-closure issues.Experience with at least one major FPGA device architecture and its associated development toolchain, such as AMD Xilinx devices with Vivado or Intel FPGA devices with Quartus, and related FPGA EDA tools such as ModelSim/QuestaSim or Synplify.Experience using Python, Tcl, C/C++, or other scripting/programming languages for automation, verification, data generation, or report analysis.Experience integrating and troubleshooting FPGA designs in simulation and laboratory hardware.Ability to develop FPGA designs with minimal supervision, communicate technical status and risks proactively, participate in technical reviews, and work effectively across engineering disciplines.U.S. citizenship.Must have interim Secret clearance prior to starting.  Once started, must have the ability to obtain and maintain a Secret security clearance. 

Preferred Qualifications

Current or active Secret or Top-Secret clearance with SCI/SAP eligibility.Domain knowledge in RF or EO/IR systems.Experience translating digital signal-processing or image-processing functions into efficient FPGA implementations.Experience with high-speed interfaces such as AXI, PCIe, Aurora, JESD, or 10G/25G/40G+ Ethernet.Experience with FPGA-based SoC architectures, such as AMD Zynq/Versal or Intel SoC FPGA devices.Experience developing and integrating FPGA/software interfaces and controls.Experience developing or prototyping algorithms using MATLAB or Simulink.Experience using SystemVerilog/UVM, cocotb, or other structured verification frameworks.Experience with clock-domain-crossing and reset-domain-crossing analysis tools or methods.Experience developing physical and timing constraints from board schematics, electrical interfaces, and system timing requirements.Experience integrating vendor IP, embedded processors, memory controllers, high-speed transceivers, and board-level interfaces.Strong hardware-level troubleshooting skills, including the use of signal generators, logic analyzers, digital oscilloscopes, protocol analyzers, and embedded FPGA debug tools such as Vivado ILA or Intel SignalTap.Experience with FPGA power estimation, utilization analysis, and design optimization.Experience with configuration-management, requirements, planning, and review tools such as Git, SVN, ClearCase, DOORS, Jira, Rally, or ClearQuest.Experience supporting controlled or formal FPGA release, qualification, production, sustainment, and field-debug activities.Demonstrated technical leadership of complex FPGA developments from concept and architecture through implementation, verification, integration, qualification, and release.Experience defining FPGA architecture, implementation strategy, interface definitions, and verification approaches for complex digital products.Experience independently resolving complex RTL, clock-domain-crossing, timing-closure, vendor-IP-integration, and hardware-debug issues.Experience leading FPGA requirements, architecture, detailed-design, test-readiness, or qualification reviews.Experience coordinating and collaborating on technical work across systems, software, hardware, verification, integration and test, manufacturing, and program-management teams.Demonstrated ability to communicate technical status, risks, tradeoffs, and recommendations to technical leadership and program stakeholders.Experience mentoring engineers, reviewing technical work products, and leading small technical teams.Ability to contribute to technical planning, estimates, risk mitigation, and proposal activities.Demonstrated adaptability, creativity, collaboration, and technical leadership, with the initiative to solve complex challenges, advance cutting-edge technologies, and drive innovation across programs and the broader product line.Demonstrated adaptability, creativity, collaboration, and independent initiative, with a passion for solving challenging problems and advancing technologies across assigned programs and products. 

Primary Level Salary Range: $119,600.00 - $179,400.00

Secondary Level Salary Range: $149,300.00 - $223,900.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate’s experience, education, skills and current market conditions.

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.